Search - verilog rs232

[Other resource] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。
Platform: | Size: 1429 | Author: saibei007 | Hits:

[Com Port] b13c_environment

Description: rs232控制器，实现rs232的环境设置，verilog编写，所有权归opencores
Platform: | Size: 63876 | Author: uknow | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[VHDL-FPGA-Verilog] 200691151948398

Description: 这是一个也介绍GPIB编程的文章以及介绍GPIB协议规范-This is a GPIB programming also introduced the article and introduce GPIB norm
Platform: | Size: 604160 | Author: 李成有 | Hits:

[Other] Verilog_PS2_RS232

Description: 实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上，并在数据接收区显示接收到的字符。串口调试终端的设置：波特率115200，一个停止位，无校验位。 -The realization of PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal and reception area in the data display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Platform: | Size: 1607680 | Author: chalin tong | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[Other] Some_design_of_interface(IIC_PS2_RS232_KEY)

Description: 一些接口电路的Verilog设计，主要包括IIC、PS2、矩阵键盘、RS232、还有一些基础试验的源代码如：除法器、多路选择器、加法器、减法器、8位优先编码器等。-Some design of interface(IIC，PS2,RS232...)
Platform: | Size: 2993152 | Author: 李皓 | Hits:

[VHDL-FPGA-Verilog] series_port

Description: 用verilog语言编写的串口收发程序，可以进行429总线数据与rs232口的通信。-With verilog program written in serial transceivers, can be 429 bus data and rs232 mouth communication.
Platform: | Size: 5120 | Author: 小刘 | Hits:

[VHDL-FPGA-Verilog] chuankoumokuai

Description: 用VERILOG实现的串口RS232自收发模块，以通过板级测试。-RS232 serial port with the VERILOG achieve self-transceiver module, through board-level test.
Platform: | Size: 8192 | Author: 闫碎猴 | Hits:

[VHDL-FPGA-Verilog] PS2UART_verilog

Description: 基于Verilog的PS/2键盘接口实现,接收PS/2键盘数据，并转换成ASCII码，通过RS232发送到PC显示。-Based on Verilog, PS/2 keyboard interface, the receiving PS/2 keyboard data and convert it into ASCII code sent to the PC through the RS232 display.
Platform: | Size: 333824 | Author: liuxingxing | Hits:

[VHDL-FPGA-Verilog] homework_final_ver1

Description: 用verilog写的PS2键盘通过RS232与PC机通信，并且通信内容通过VGA显示-PS2 keyboard with verilog to write computer communication via RS232 with the PC and the communication content through VGA display
Platform: | Size: 4268032 | Author: 邱柳钦 | Hits:

[VHDL-FPGA-Verilog] RS232_ysd

Description: RS232串口通信程序，经过开发板验证，程序正确无误，是采用Verilog语言编写的-RS232 serial communication program, through the development board verification, the program is correct, is written using Verilog
Platform: | Size: 1357824 | Author: 王红 | Hits:

[VHDL-FPGA-Verilog] uart_test

Description: Verilog 基于FPGA的直接RS232串口测试-Verilog FPGA-based test of direct RS232 serial port
Platform: | Size: 588800 | Author: yuanjun | Hits:

[VHDL-FPGA-Verilog] async_transmitter

Description: verilog语言，RS232异步发送模块-verilog language, RS232 asynchronous transmit module
Platform: | Size: 1024 | Author: 何沐 | Hits:

[VHDL-FPGA-Verilog] VerilogRS232

Description: 基于Verilog 语言FPGA RS232 通信程序,已测试通过-FPGA RS232 Communication Program using Verilog Hard Description Language
Platform: | Size: 1346560 | Author: 刘刚 | Hits:

[VHDL-FPGA-Verilog] S10_PS2_RS232

Description: verilog+ps2+rs232..不错的源代码-verilog+ ps2+ rs232
Platform: | Size: 1613824 | Author: 王半田 | Hits:

[VHDL-FPGA-Verilog] uart_fpga4fun

Description: rs232通信代码，在自己的xilinx开发板上已验证通过-rs232 code with verilog has been verified
Platform: | Size: 232448 | Author: 许磊 | Hits:

[VHDL-FPGA-Verilog] async_transmitter

Description: RS232。串行通信接口RS232，verilog -failed to translate
Platform: | Size: 1024 | Author: 韩小 | Hits:

[VHDL-FPGA-Verilog] uartverilog

Description: 该程序是Verilog写的串口收发程序，具有基本的收发功能，经过验证，能使初学者很好了解rs232，和Verilog-The program is written in Verilog serial transceiver program, with the basic send and receive functions, proven, good for beginners can understand rs232, and Verilog
Platform: | Size: 38912 | Author: 徐飞 | Hits:

[VHDL-FPGA-Verilog] Serial-debugging

Description: 本文分析RS232 串口通信的原理，介绍Verilog 模块调用的方法-This paper analyzes the principle of the RS232 serial communication, introduction to the Verilog module calls the method
Platform: | Size: 516096 | Author: dltt | Hits:

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[Other resource] UART

[Com Port] b13c_environment

[VHDL-FPGA-Verilog] generic_fifo

[VHDL-FPGA-Verilog] 200691151948398

[Other] Verilog_PS2_RS232

[Com Port] UART

[Other] Some_design_of_interface(IIC_PS2_RS232_KEY)

[VHDL-FPGA-Verilog] series_port

[VHDL-FPGA-Verilog] chuankoumokuai

[VHDL-FPGA-Verilog] PS2UART_verilog

[VHDL-FPGA-Verilog] homework_final_ver1

[VHDL-FPGA-Verilog] RS232_ysd

[VHDL-FPGA-Verilog] uart_test

[VHDL-FPGA-Verilog] async_transmitter

[VHDL-FPGA-Verilog] VerilogRS232

[VHDL-FPGA-Verilog] S10_PS2_RS232

[VHDL-FPGA-Verilog] uart_fpga4fun

[VHDL-FPGA-Verilog] async_transmitter

[VHDL-FPGA-Verilog] uartverilog

[VHDL-FPGA-Verilog] Serial-debugging

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